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The ASIC design environment is used for educational purposes in lectures and student laboratories. Digital ASIC design is performed with the Cadence framework.
Students are trained on the front end design flow including HDL design (VHDL or Verilog), simulation, verification, synthesis and static timing analysis as well as the basic back end design flow.
The environment is used in the courses 'Digital ASIC Design Tools Lab', 'SystemVerilog for Design' and 'SystemVerilog for Verification'.
Power Management ICs …
Compact Wheel Loaders …
Microprocessor design …