(06/2022) Lessons learned from teaching during the global Corona pandemic.


(03/2022) New elective subject 'SystemVerilog for Verification' available.


(01/2022) Annual report 2021 avaliable for download.
Enjoy reading!


Research & Development


  • Near-/In-Memory Computing
  • Digital HDL Design
  • Massively Parallel EM-Simulation
  • Computational Optics
  • Floating Point Unit
  • RISC-V

    a free ISA, by the UC Berkeley with available open source cores for education purpose and product development.


  • Optical detector
  • Automation and Control

    "No recent activities."


    "Hybrid modelling and control for a Brine Heater of a Multi-Stage-Flash desalination plant implemented with Matlab."


  • Presentations & Downloads

    "EM simulation with CUDA/C/C++/QT, Matlab and Delphi."


    "SOI detector layout example in SKILL."


  • Thesis & Internships

    "List of open and completed bachelor and master thesis and internships."


Academic Teaching


Microprocessor architecture


Cadence design framework

As an academic organization and user of a Cadence academic license agreement, we hereby make our work visible.

The ASIC design environment is used for educational purposes in lectures and student laboratories. Digital ASIC design is performed with the Cadence framework.

Students are trained on the front end design with HDL (VHDL or Verilog), simulation with INCISIVE, synthesis with GENUS and static timing analysis with TEMPUS.