Introduction to the Digital ASIC Design Flow

Name of the course	Online	Lecture	Exercises	Lab
Digital ASIC Design Flow Lab	✓	✗	✗	✓

The 'Digital ASIC Design Flow Lab' is a set of practical laboratories for prospective engineering managers and an orientation for individuals interested in becoming a digital ASIC design R&D engineer. The course introduces the major design steps of digital ASIC design projects. The lab exercises focus on the design flow and the design environment from front-end to back-end. Important development procedures and milestones in digital ASIC design projects are explained. The course material is in English. The course language is usually German.

To benefit from attendance it is recommended to have skills in Digital Engineering and Electrical Engineering as well as some experience with the Unix operating systen and shell script. Knowledge in semiconductor technology is an advantage but not a must.

The lab is a guided online course offered in a virtual classroom. Students have to be present during lab appointments to deliver performance and complete the course successfully. A physical presence at the campus not required to complete the lab exercises. The course is as such barrier-free.

The course is founded on the Cadence Design Environment. During lab exercises participants learn to understand the sequence of design steps and how these steps are mapped to the tools along the design flow.

Having completed the course successfully, participants should understand the digital design flow for Application Specific Integrated Circuits (ASICs). They should be able to identify and track a development process, verify a successful use of tools and how to interpret the outputs to some extent.

Participants work on ready-to-run design environments and ready-to-use designs along the entire course. It is NOT necessary for participants to develop designs or configure tools. The course is supposed to introduce the design flow to prospective engineering managers and qualify them to create reasonable work packages, time plans, track milestones etc. in ASIC design projects. It is out of the scope of this course to introduce how a design is developed and how individual tools can be configured to address individual characteristics of a design.

The output of an exercise can be found here.

Please watch before registration!

This course is focused on ASICs.
What is an ASIC, FPGA, SOC? [w3]

This course is focused on the digital ASIC design flow.
What is the digital ASIC Design Flow? [w3]

Lab Exercises

Num	Description
1	Introduction to the Digital Design Flow
2	Introduction to the Digital ECO Flow
3	Static Timing Analysis of a Dual-Tone Multi-Frequency Reveiver (DMTF)
4	Synthesis of a Dual-Tone Multi-Frequency Reveiver (DMTF)
5	Power Profiling of a 10-bit CPU design at RTL level
6	Low-power implementation of a SiFive P670 RISC-V CPU core
7	3D Integration of a two-die RISC-V design
8	RTL to GDSII implementation of a tiny Digital Signal Processor (DSP)

Participants work on the labs remotely on a universities server using individual VNC sessions. Attendance from a computer room at the university is possible but a personal device is recommended to work from every place and outside the opening hours.

Literature

[1] CMOS VLSI Design, 4th edition by Weste Neil Harris David, 2010, ISBN-13 978-0321547743
[2] Application Specific Integrated Circuits, Michael Smith, 1997, ISBN-13 978-0201500226, [w3] or [w3]
[3] Cadence documentation and training material