Digital ASIC Design Laboratories

Num	Name of the course	Online	Lecture	Exercises	Lab
1	Introduction to the Digital ASIC Design Flow	✓	✓	✗	✓
2	Digital ASIC Design Lab	✓	✗	✓	✓

Context

'Introduction to the Digital ASIC Design Flow' is an introductory course in the Bachelor programs and requires just a basic knowledge in Electrical Engineering and Physics.

'Digital ASIC Design Lab' is an advanced course in the Bachelor programs or an introductory course in the Master programs.

Preliminary courses/knowledge for the course 'Digital ASIC Design Lab':

• Introduction to Electrical Engineering [w3]
• Introduction to Digital Engineering [w3]
• Basic knowledge in Unix/Linux and shell script

Recommended Preliminary courses:

• Introduction to Digital Circuit Design [w3]
• Microprocessor Architecture [w3]

Follow-on courses:

• SystemVerilog for Design [w3]
• SystemVerilog for Verification [w3]

1. Details 'Introduction to the Digital ASIC Design Flow'

The course 'Introduction to the Digital ASIC Design Flow' is a third semester course for students of Bachelor programs and with basic knowledge in Electrical Engineering and Physics. The course provides an orientation for Engineering or Industrial Engineering students to decide on their field of specialization. All laboratories are on introductory level and supported by small units of lecture. The focus is on the investigation of technical coherences by practical execution.

Participants work on different ready-to-run digital ASIC design flows and on ready-to-use designs during the entire course. It is not necessary to develop new designs or to setup and configure a design flow from scratch. Participants investigate the flow of design data along the chain of tools and how the results develop along the process.

The course is offered barrier-free in a virtual classroom. Presence is mandatory to complete the course successfully. Physical presence at the campus is possible but not required.

Num	Description - 'Introduction to the Digital ASIC Design Flow'
1	Hardware Design and Simulation
2	Digital Hardware Synthesis
3	Static Timing Analysis
4	Floorplanning and Layout
5	Timing Closure
6	Engineering Change Orders

2. Details 'Digital ASIC Design Lab'

The course 'ASIC Design Flow Lab' is an advanced course on digital ASIC design in the finals of Bachelor programs or in the beginnings of Master programs. The course is intended for prospective digital ASIC design engineers or engineering managers in the semiconductor research and development. The laboratories include basic and advanced design steps along the entire development process. It highlights the most critical engineering corners and project milestones.

The course aims for engineering managers to define work packages, create time plans, interpret engineering outputs and track development cycles. Candidates with a sound background in digital engineering get introduced to the technical complexity of digital ASIC engineering. All participants are trained on a contemporary up-to-date design environment as utilized in industry.

The course is founded on the Cadence Design Environment using the Cadence Acacdemic License. This guarantees a full-functional set of tools at industrial standard, excellent documentation and support as well as regular updates so that the course offers an up-to-date design environment at all times.

The course is offered barrier-free in a virtual classroom. Presence is mandatory to complete the course successfully. Physical presence at the campus is possible but not required.

Participants work on different ready-to-run digital ASIC design flows and on ready-to-use designs during the entire course. Participants modify designs and/or process configurations to adapt results to specific design goals. Participants investigate the results on design flow modifications along the entire tools chain.

The course offers lab exercises on the general design flow as well as on specific design aspects, e.g. Engineering Change Orders, Low Power, 3D-Integration. The output of a sample exercise can be found here.

Num	Description - 'ASIC Design Flow Lab'
1	Digital Design Flow and Digical ECO Flow
2	RTL to GDSII implementation of a tiny Digital Signal Processor (DSP)
3	Static Timing Analysis of a Dual-Tone Multi-Frequency Reveiver (DMTF)
4	Synthesis of a Dual-Tone Multi-Frequency Reveiver (DMTF)
5	Power Profiling of a 10-bit CPU design at RTL level
6	Low-power implementation of a SiFive P670 RISC-V CPU core

Literature

[1] CMOS VLSI Design, 4th edition by Weste Neil Harris David, 2010, ISBN-13 978-0321547743
[2] Application Specific Integrated Circuits, Michael Smith, 1997, ISBN-13 978-0201500226, [w3] or [w3]
[3] Cadence documentation and training material