Coverage Summary Report, Instance-Based
Top Level SummaryLegend and Help
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv |
Coverage Summary Report, Instance-Based
| Overall | Overall Covered | Block | Expression | Toggle | FSM State | FSM Transition | Assertion | CoverGroup | CoverGroup Covered | name |
|---|---|---|---|---|---|---|---|---|---|---|
| 20.00% | 16.67% (2/12) | 40.00% (2/5) | n/a | 0.00% (0/7) | n/a | n/a | n/a | n/a | n/a | leading_zero_compressor_I |
Uncovered Block Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv Number of uncovered blocks: 3 of 5 Number of unreachable blocks: 0 |
Count Block Line Kind Origin Source Code
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0 3 15 a case item of 13 2'b01: compressed = {1'b0,left};
0 4 16 a case item of 13 2'b10: compressed = {2'b01,right[WIDTH-2:0]};
0 5 17 a case item of 13 2'b11: compressed = {1'b1,{WIDTH{1'b0}}};
Uncovered Expression Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv Number of uncovered expressions: 0 of 0 Number of unreachable expressions: 0 |
index | grade | line | expression ------------------------------------------------------------------------------------- 0 items found
Uncovered Toggle Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv Number of uncovered signal bits: 7 of 7 Number of unreachable signal bits: 0 Number of signal bits partially toggled(rise): 0 of 7 Number of signal bits partially toggled(fall): 0 of 7 |
Hit(Full) Hit(Rise) Hit(Fall) Signal ----------------------------------------------------------- 0 0 0 left[1] 0 0 0 left[0] 0 0 0 right[1] 0 0 0 right[0] 0 0 0 compressed[2] 0 0 0 compressed[1] 0 0 0 compressed[0]
Uncovered Fsm Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv |
0 items found
Uncovered Assertion Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv Number of uncovered assertions: 0 of 0 |
Finished Failed Assertion Line Source Code ------------------------------------------------------------------------------------ 0 items found
Uncovered CoverGroup Detail Report, Instance Based
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Instance name: tb_top.fma_top_I.leading_zero_anticipator_I.leading_zero_counter_I.compress_tree_depth[0].compress_tree_width[1].genblk1.leading_zero_compressor_I Type name: leading_zero_compressor File name: /home/mfertig/riscv2/riscv_FPU/external/riscv_bb/leading_zero_counter/leading_zero_compressor.sv Number of uncovered cover bins: 0 of 0 |
0 items found